Performance Analysis of Clock-Regulated Queues with Output Multiplexing in Three Different 2 x 2 Crossbar Switch Architectures

Abstract

Switches in interconnection networks for highly parallel shared memory computer systems may be implemented with different internal buffer structures. For a 2×2 synchronous switch, previous studies have often assumed a switch composed of two queues, one at each output, each of which has unbounded size and may accept two inputs every clock cycle. Hardware… (More)
DOI: 10.1016/0743-7315(92)90041-K

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