Performance Analysis of 60-nm Gate-Length III–V InGaAs HEMTs: Simulations Versus Experiments

@article{Neophytou2008PerformanceAO,
  title={Performance Analysis of 60-nm Gate-Length III–V InGaAs HEMTs: Simulations Versus Experiments},
  author={Neophytos Neophytou and Titash Rakshit and Mark Lundstrom},
  journal={IEEE Transactions on Electron Devices},
  year={2008},
  volume={56},
  pages={1377-1387}
}
An analysis of recent experimental data for high-performance In0.7Ga0.3As high electron mobility transistors (HEMTs) for logic applications is presented. By using a fully quantum mechanical ballistic model, we simulate In0.7Ga0.3As HEMTs with gate lengths of LG = 60, 85, and 135 nm and compare the result to the measured IV characteristics, including drain-induced barrier lowering, subthreshold swing, and threshold voltage variation with gate insulator (wide-bandgap barrier layer) thickness, as… 

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