Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems

@inproceedings{Inoue2000PerformanceEnergyEO,
  title={Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems},
  author={Koji Inoue and Koji Kai and Kazuaki Murakami},
  booktitle={Intelligent Memory Systems},
  year={2000}
}
Integrating main memory (DRAM) and processors into a single chip, or merged DRAM/logic LSI, makes it possible to exploit high on-chip memory bandwidth by widening on-chip bus and on-chip DRAM array. In addition, from energy point of view, the integration brings a significant improvement by decreasing the number of off-chip accesses. 

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Key Quantitative Results

  • While the improvements of conventional approach of increasing associativity or capacity are only from 25 % to 30 %.

Citations

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CITES BACKGROUND

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