Performance, degradation monitors, and reliability of the CHISEL injection regime

@article{Driussi2004PerformanceDM,
  title={Performance, degradation monitors, and reliability of the CHISEL injection regime},
  author={Francesco Driussi and David Esseni and Luca Selmi},
  journal={IEEE Transactions on Device and Materials Reliability},
  year={2004},
  volume={4},
  pages={327-334}
}
This work reviews recent results concerning the performance and reliability of the channel initiated secondary electron (CHISEL) injection regime, often used to boost the programming speed of Flash memories. In order to relate the CHISEL behavior to the physical conditions existing in the device, the injection efficiency of CHISEL is studied on single transistors. A comparison between the degradation in the CHISEL injection and in the channel hot electron (CHE) stress regime has been also… CONTINUE READING

References

Publications referenced by this paper.
Showing 1-10 of 42 references

A better understanding of substrate enhanced gate current in MOSFET’s and flash cells, part I: Phenomenological aspects

  • D. Esseni, L. Selmi
  • IEEE Trans. Electron Devices, vol. 46, pp. 369…
  • 1999
Highly Influential
4 Excerpts

CHISEL programming operation of scaled NOR flash EEP- ROMs—Effect of voltage scaling, device scaling, and technological parameters

  • N. R. Mohapatra, D. R. Nair, S. Mahapatra, V. Rao, S. Shukuri, J. Bude
  • IEEE Trans. Electron Devices, vol. 50, pp. 2104…
  • 2003
1 Excerpt

Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs

  • N. R. Mohapatra, S. Mahapatra, V. R. Rao, S. Shukuri, J. D. Bude
  • Proc. Int. Reliability Physics Symp., 2003, pp…
  • 2003
1 Excerpt

CHISEL flash EEPROM—Part I: Performance and scaling

  • S. Mahapatra, S. Shukuri, J. Bude
  • IEEE Trans. Electron Devices, vol. 49, pp. 1296…
  • 2002
3 Excerpts

CHISEL flash EEPROM—Part II: Reliability

  • S. Mahapatra, S. Shukuri, J. Bude
  • IEEE Trans. Electron Devices, vol. 49, pp. 1302…
  • 2002
2 Excerpts

Damage generation and location in n- and pMOSFET’s biased in the substrate enhanced gate current regime

  • F. Driussi, D. Esseni, L. Selmi, F. Piazza
  • IEEE Trans. Electron Devices, vol. 49, pp. 787…
  • 2002
1 Excerpt

On interface and oxide degradation in VLSI MOSFETs—Part II: Fowler-Nordheim stress regime

  • D. Esseni, J. D. Bude, L. Selmi
  • IEEE Trans. Electron Devices, vol. 49, pp. 253…
  • 2002
1 Excerpt

A 180 nm secondary electron injection flash device

  • G. Xue, J. Van Houdt, L. Haspeslagh, D. Wellekens, B. Keppens, H. Maes
  • Proc. Non Volatile Memory Workshop, 2001, pp. 62…
  • 2001

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