Peak Crosstalk Noise Estimation in CMOS VLSI Circuits

Abstract

|Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or less than the time of ight delay of the signal through the interconnect. In this discussion, a linear resistor model is used to approximate the CMOS driver stage, and the CMOS receiver is… (More)

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