Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation

Abstract

This paper shows stream-oriented FPGA implementation of the machine-learned Features from Accelerated Segment Test (FAST) corner detection, which is used in the parallel tracking and mapping (PTAM) for augmented reality (AR). One of the difficulties of compact hardware implementation of the FAST corner detection is a matching process with a large number of corner patterns. We propose corner pattern compression methods focusing on discriminant division and pattern symmetry for rotation and inversion. This pattern compression enables implementation of the corner pattern matching with a combinational circuit. Our prototype implementation achieves real-time execution performance with 7-9% of available slices of a Virtex-5 FPGA.

DOI: 10.1109/FPL.2011.94

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Cite this paper

@article{Dohi2011PatternCO, title={Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation}, author={Keisuke Dohi and Yuji Yorita and Yuichiro Shibata and Kiyoshi Oguri}, journal={2011 21st International Conference on Field Programmable Logic and Applications}, year={2011}, pages={478-481} }