• DOI:10.1038/s41534-022-00600-9
• Corpus ID: 247011839

Path toward manufacturable superconducting qubits with relaxation times exceeding 0.1 ms

@article{Verjauw2022PathTM,
  title={Path toward manufacturable superconducting qubits with relaxation times exceeding 0.1 ms},
  author={Jeroen Verjauw and Rohith Acharya and Jacques Van Damme and Tsvetan Ivanov and Daniel Perez Lozano and Fahd A. Mohiyaddin and Danny Wan and Julien Jussot and A. M. Vadiraj and Massimo Mongillo and Marc M. Heyns and Iuliana P. Radu and Bogdan Govoreanu and A. Poto{\vc}nik},
  journal={npj Quantum Information},
  year={2022},
  volume={8},
  pages={1-7}
}

• J. Verjauw, R. Acharya, +11 authors A. Potočnik
• Published 21 February 2022
• Physics
• npj Quantum Information

As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become apparent. To benefit from the advanced process control in industry-scale CMOS fabrication facilities, different processing methods will be required. In particular, the double-angle evaporation and lift-off techniques used for current, state-of-the-art superconducting qubits are generally incompatible with modern-day manufacturable processes. Here, we demonstrate a fully CMOS compatible qubit fabrication method, and show results from overlap Josephson junction devices with long coherence and relaxation times, on par with the state-of-the-art. We experimentally verify that Argon milling—the critical step during junction fabrication—and a subtractive-etch process nevertheless result in qubits with average qubit energy relaxation times T 1 reaching 70 µs, with maximum values exceeding 100 µs. Furthermore, we show that our results are still limited by surface losses and not, crucially, by junction losses. The presented fabrication process, therefore, heralds an important milestone towards a manufacturable 300 mm CMOS process for high-coherence superconducting qubits and has the potential to advance the scaling of superconducting device architectures.