Path delay fault simulation on large industrial designs

@article{Natarajan2006PathDF,
  title={Path delay fault simulation on large industrial designs},
  author={Suriyaprakash Natarajan and Srinivas Patil and Sreejit Chakravarty},
  journal={24th IEEE VLSI Test Symposium},
  year={2006},
  pages={6 pp.-23}
}
Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel multi-cycle path delay fault simulator. Our experiments show that path delay fault simulation run-time grows linearly with path list size. Contrary to commonly held notion that path delay fault simulation is more expensive than stuck-at fault… CONTINUE READING