Path-Oriented Test Data Generation of Behavioral VHDL Description

Abstract

The validation of HDL descriptions before their synthesis is one of the principal problems related to the top-down design process of complex circuits. This task can be accomplished according two approaches: formal verification or simulation based validation. Because formal verification, in spite of recent progress, is only feasible for small descriptions… (More)
DOI: 10.1109/DELTA.2002.994655

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