Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors
@article{Navarro1987PartitioningAE,
title={Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors},
author={Juan J. Navarro and Jos{\'e} Mar{\'i}a Llaber{\'i}a and Mateo Valero},
journal={Computer},
year={1987},
volume={20},
pages={77-89}
}Many scientific and technical applications require high computing speed; those involving matrix computations are typical. For applications involving matrix computations, algorithmically specialized, high-performance, low-cost architectures have been conceived and implemented. Systolic array processors (SAPs) are a good example of these machines. An SAP is a regular array of simple processing elements (PEs) that have a nearest-neighbor interconnection pattern. The simplicity, modularity, and…
110 Citations
Mapping regular recursive algorithms to fine-grained processor arrays
- Computer Science
- 1994
A systematic parameter-based method, called the General Parameter Method (GPM), to design optimal, lower-dimensional processor arrays for uniform dependence algorithms has been developed and it can found that the system yield improves with the area of the coprocessor when chip yield decreases as the inverse square of the clock frequency.
A methodology for fast scheduling of partitioned systolic algorithms
- Business, Computer ScienceJ. VLSI Signal Process.
- 1995
Efficient scheduling techniques are developed for the partitioning problem, i.e. problems with size that do not match the array size, exploiting the fact that after LPGS and LSGP partitioning, the locality constraints are less stringent allowing for more flexibility in the choice of algorithms and inter-processor communication.
On Mapping Systolic Algorithms onto the Hypercube
- Computer ScienceIEEE Trans. Parallel Distributed Syst.
- 1990
Several optimal implementations of algorithms given for one-way one- and two-dimensional systolic arrays for efficient communication for a fixed-size hypercube architecture are described.
Arrays For Partitioned Matrix Algorithms: Tradeoffs Between Cell Storage And Cell Bandwidth
- Computer ScienceOptics & Photonics
- 1989
A graph-based partitioning method for designing systolic arrays for matrix computations is extended to apply it to processing elements with a small local memory, which produces a reduction in the cell communication bandwidth and facilitates the use of pipelining within cells.
Linear Array For Efficient Execution Of Partitioned Matrix Algorithms
- Computer ScienceOptics & Photonics
- 1989
We propose a class-specific linear array suitable for partitioned execution of matrix algorithms, which achieves high efficiency, exploits pipelining within cells in a simple manner, has off cells…
Designing a Scalable Processor Array for Recurrent Computations
- Computer ScienceIEEE Trans. Parallel Distributed Syst.
- 1997
The study demonstrates the feasibility of a low-cost, memory bandwidth-limited, and scalable coprocessor system for evaluating recurrent algorithms with uniform dependencies.
A design methodology for fixed-size systolic arrays
- Computer Science[1990] Proceedings of the International Conference on Application Specific Array Processors
- 1990
The authors present a methodology to design fixed-size systolic arrays. It allows a systematic and hierarchical mapping of full-size arrays to fixed-size arrays. Two processor-clustering techniques…
Parallel SOLVE for direct circuit simulation on a transputer array
- Computer ScienceProceedings of 3rd International Conference on High Performance Computing (HiPC)
- 1996
A block partitionable sparse matrix solution algorithm in which a matrix is divided into equal size blocks, and blocks are assigned to different processors for parallel execution, which maximizes concurrency and minimizes communication between processors.
Novel Scheduling Scheme For Systolic Array Partitioning Problem
- Computer ScienceWorkshop on VLSI Signal Processing
- 1992
This paper proposes a novel two-level scheduling scheme of the systolic array partitioning problem which enables significant reduction in overall computing time and incorporates a more realistic computation model in which the inter-processor communication delay is treated separately from the node computation delay.
References
SHOWING 1-10 OF 18 REFERENCES
Computing size-independent matrix problems on systolic array processors
- Computer ScienceISCA '86
- 1986
A methodology to transform dense to band matrices is presented, and allows the implementation of solutions to problems with any given size, by means of contraflow systolic arrays, originally proposed by H.T. Kung.
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
- Computer ScienceIEEE Transactions on Computers
- 1986
A technique for partitioning and mapping algorithms into VLSI systolic arrays is presented and an approach to algorithm partitioning which is also based on algorithm transformations is presented.
VLSI Array processors
- Computer ScienceIEEE ASSP Magazine
- 1985
A general overview of VLSI array processors is provided and a unified treatment from algorithm, architecture, and application perspectives is provided.
A Versatile Systolic Array for Matrix Computations
- Computer ScienceISCA
- 1985
This paper presents a feedback systolic array system for matrix computations which, in addition to being able to produce high throughput, has improved utility.
Why systolic architectures?
- Computer ScienceComputer
- 1982
The basic principle of systolic architectures is reviewed and it is explained why they should result in cost-effective, highperformance special-purpose systems for a wide range of problems.
Algorithm partition for a fixed-size VLSI architecture using space-time domain expansion
- Computer Science1985 IEEE 7th Symposium on Computer Arithmetic (ARITH)
- 1985
A computational model and a partition rule are proposed which can be easily used to partition any recursive computation problem suited to the space-time domain expansion method so it can be solved on fixed-size VLSI architectures.
Wafer-scale integration and two-level pipelined implementations of systolic arrays
- Computer ScienceJ. Parallel Distributed Comput.
- 1984
Systolic Arrays for (VLSI).
- Computer Science
- 1978
A systolic system is a network of processors which rhythmically compute and pass data through the system, and almost all processors used in the networks are identical, so that a regular flow of data is kept up in the network.