Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors
@article{Navarro1987PartitioningAE, title={Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors}, author={Juan J. Navarro and Jos{\'e} Mar{\'i}a Llaber{\'i}a and Mateo Valero}, journal={Computer}, year={1987}, volume={20}, pages={77-89} }
Many scientific and technical applications require high computing speed; those involving matrix computations are typical. For applications involving matrix computations, algorithmically specialized, high-performance, low-cost architectures have been conceived and implemented. Systolic array processors (SAPs) are a good example of these machines. An SAP is a regular array of simple processing elements (PEs) that have a nearest-neighbor interconnection pattern. The simplicity, modularity, and…
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References
SHOWING 1-10 OF 18 REFERENCES
Computing size-independent matrix problems on systolic array processors
- Computer ScienceISCA '86
- 1986
A methodology to transform dense to band matrices is presented, and allows the implementation of solutions to problems with any given size, by means of contraflow systolic arrays, originally proposed by H.T. Kung.
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
- Computer ScienceIEEE Transactions on Computers
- 1986
A technique for partitioning and mapping algorithms into VLSI systolic arrays is presented and an approach to algorithm partitioning which is also based on algorithm transformations is presented.
VLSI Array processors
- Computer ScienceIEEE ASSP Magazine
- 1985
A general overview of VLSI array processors is provided and a unified treatment from algorithm, architecture, and application perspectives is provided.
A Versatile Systolic Array for Matrix Computations
- Computer ScienceISCA
- 1985
This paper presents a feedback systolic array system for matrix computations which, in addition to being able to produce high throughput, has improved utility.
Why systolic architectures?
- Computer ScienceComputer
- 1982
The basic principle of systolic architectures is reviewed and it is explained why they should result in cost-effective, highperformance special-purpose systems for a wide range of problems.
Algorithm partition for a fixed-size VLSI architecture using space-time domain expansion
- Computer Science1985 IEEE 7th Symposium on Computer Arithmetic (ARITH)
- 1985
A computational model and a partition rule are proposed which can be easily used to partition any recursive computation problem suited to the space-time domain expansion method so it can be solved on fixed-size VLSI architectures.
Wafer-scale integration and two-level pipelined implementations of systolic arrays
- Computer ScienceJ. Parallel Distributed Comput.
- 1984
Systolic Arrays for (VLSI).
- Computer Science
- 1978
A systolic system is a network of processors which rhythmically compute and pass data through the system, and almost all processors used in the networks are identical, so that a regular flow of data is kept up in the network.