Partitioned register files for VLIWs: a preliminary analysis of tradeoffs

  title={Partitioned register files for VLIWs: a preliminary analysis of tradeoffs},
  author={Andrea Capitanio and Nikil D. Dutt and Alexandru Nicolau},
An ideal VLIW architecture requires a large multiport register file that is currently not realizable in practice. We analyze a Limited Connectivity VLIW architecture as a realizable alternative that limits the number of ports. We present a fine-grain code partitioning method for this model. The partitioning scheme was applied to a number of standard benchmarks by varying the number ports on a RF, the number of partitions and the communication bandwidth between partitions. We present these… CONTINUE READING
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