Partial resolution in branch target buffers

@inproceedings{Fagin1995PartialRI,
  title={Partial resolution in branch target buffers},
  author={B. Fagin and K. Russell},
  booktitle={MICRO 1995},
  year={1995}
}
Branch target buffers, or BTBs, are small caches for recently accessed program branching information. Like data caches, the set of intercepted addresses is divided into equivalence classes based on the low order bits of an address. Unlike data caches, however, complete resolution of a single address from within an equivalence class is not required for correct program execution. Substantial savings are therefore possible by employing partial resolution, using fewer tag bits than necessary to… Expand
Partial Resolution in Branch Target Buffers
  • B. Fagin
  • Computer Science
  • IEEE Trans. Computers
  • 1997
Cost-Efficient Branch Target Buffers
Phantom-BTB: a virtualized branch target buffer design
Energy Reduction of BTB by Focusing on Number of Branches per Cache Line
Tag overflow buffering: an energy-efficient cache architecture
Two-Level Address Storage and Address Prediction (Research Note)
Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching
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References

SHOWING 1-10 OF 40 REFERENCES
Fast and accurate instruction fetch and branch prediction
Branch Target Buffer Design and Optimization
Improving the accuracy of dynamic branch prediction using branch correlation
A comparison of dynamic branch predictors that use two levels of branch history
A schedular-sensitive global register allocator
An effective programmable prefetch engine for on-chip caches
  • Tien-Fu Chen
  • Computer Science
  • MICRO 1995
  • 1995
Register allocation over the program dependence graph
Postpass Code Optimization of Pipeline Constraints
...
1
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3
4
...