Partial Scan Test Generation for Asynchronous Circuits Based On Breaking Global Loops

Abstract

Asynchronous circuits without global clocks are hard to test. Scan design methods provide an effective way to test these circuits. Full scan design seems to be a perfect alternative but at the cost of area overhead. So partial scan based design helps to overcome this area overhead problem and giving a better fault coverage. This paper presents a partial… (More)

Topics

3 Figures and Tables

Slides referencing similar topics