• Engineering
  • Published 2004

Pareto Optimal Modeling for Efficient PLL Optimization

@inproceedings{Tiwary2004ParetoOM,
  title={Pareto Optimal Modeling for Efficient PLL Optimization},
  author={Saurabh K. Tiwary and Senthil N. Velu and Rob A. Rutenbar and Tamal Mukherjee},
  year={2004}
}
Simulation-based synthesis tools for analog circuits [1,2] face a problem extending their sizing/biasing methodology to larger block-level designs such as phase lock loops or converters: the time to fully evaluate (i.e., to fully simulate) each complete circuit solution candidate is prohibitive inside a numerical optimization loop. In this paper, we show how to circumvent this problem with a careful mix of behavioral models for less-critical parts of the block, and pareto-optimal trade-off… CONTINUE READING

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