Parametrizable Architecture for the Motion Estimator Chip

Abstract

In this paper a parametrizable architecture of a motion estimator is presented. The architecture supports the H.263 standard but can be adopted for other video standards as well. The parameters by which the motion estimator is described allow for a variety of architecture conngurations. The parameters specify the level of parallelism, the algorithmic pipelining, and the use of conngurable cache memories. VLSI implementation is performed by Cathedral-2/3, a high-level synthesis environment for high-speed applications.

Cite this paper

@inproceedings{Cmar1996ParametrizableAF, title={Parametrizable Architecture for the Motion Estimator Chip}, author={Radim Cmar and Serge Vernalde}, year={1996} }