In this paper we propose a novel method for estimating the gain, DC offset and sample timing mismatches between component ADCs in a Parallel Interleaved ADC. We propose the use of a reference ADC, operating at a lower rate, that precludes the need for any calibration period. The reference ADC is clocked using a novel scheme to provide reference samples that are used by the estimation algorithm We propose the use of Least Squares (LS) based approach for correcting the gain and DC offset mismatches as well as a bisection search and a fixed step adaptation for estimating/correcting the sample timing offset. These algorithms ensure fast initial convergence and good steady state tracking with little implementation overhead. Simulation results are presented to illustrate the efficacy of these techniques.