Parallelizing FPGA placement using Transactional Memory

  title={Parallelizing FPGA placement using Transactional Memory},
  author={Steven Birk and J. Gregory Steffan and Jason Helge Anderson},
  journal={2010 International Conference on Field-Programmable Technology},
To capitalize on the growing abundance of multicore hardware, FPGA vendors have begun to parallelize the most compute intensive algorithms in their CAD software. However, parallelization is a painstaking and hence expensive process that limits the number of algorithms that can be cost-effectively parallelized. Transactional Memory (TM) promises an easier-to-use alternative to locks for critical sections in threaded code—allowing programmers to avoid deadlocks and data races, and also allowing… CONTINUE READING

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