Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems

  title={Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems},
  author={Onur Mutlu and Thomas Moscibroda},
  journal={2008 International Symposium on Computer Architecture},
In a chip-multiprocessor (CMP) system, the DRAM system isshared among cores. In a shared DRAM system, requests from athread can not only delay requests from other threads by causingbank/bus/row-buffer conflicts but they can also destroy other threads’DRAM-bank-level parallelism. Requests whose latencies would otherwisehave been overlapped could effectively become serialized. As aresult both fairness and system throughput degrade, and some threadscan starve for long time periods.This paper… CONTINUE READING
Highly Influential
This paper has highly influenced 53 other papers. REVIEW HIGHLY INFLUENTIAL CITATIONS
Highly Cited
This paper has 557 citations. REVIEW CITATIONS


Publications citing this paper.
Showing 1-10 of 372 extracted citations

558 Citations

Citations per Year
Semantic Scholar estimates that this publication has 558 citations based on the available data.

See our FAQ for additional information.


Publications referenced by this paper.
Showing 1-9 of 9 references

Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order. U.S

  • W. K. Zuravleff, T. Robinson
  • Patent Number
  • 1997
Highly Influential
8 Excerpts

Various optimizers for single stage production

  • W. E. Smith
  • Naval Research Logistics Quarterly,
  • 1956
Highly Influential
3 Excerpts

Similar Papers

Loading similar papers…