Parallel software for inductance extraction

Abstract

The next generation VLSI circuits will be designed with millions of densely packed interconnect segments on a single chip. Inductive effects between these segments begin to dominate signal delay as the clock frequency is increased. Modern parasitic extraction tools to estimate the onchip inductive effects with high accuracy have had limited impact due to… (More)
DOI: 10.1109/ICPP.2004.1327946

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