Parallel reduced area multipliers

@article{Bickerstaff1995ParallelRA,
  title={Parallel reduced area multipliers},
  author={K'Andrea C. Bickerstaff and Michael J. Schulte and Earl E. Swartzlander},
  journal={VLSI Signal Processing},
  year={1995},
  volume={9},
  pages={181-191}
}
As developed by Wallace and Dadda, a method for high-speed, parallel multiplication is to generate a matrix of partial products and then reduce the partial products to two numbers whose sum is equal to the final product. The resulting two numbers are then summed using a fast carry-propagate adder. This paper presents Reduced Area multipliers, which employ a modified reduction scheme that results in fewer components and less interconnect overhead than either Wallace or Dadda multipliers. This… CONTINUE READING
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