Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding

@article{Rister2014ParallelPO,
  title={Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding},
  author={Blaine Rister and Pekka J{\"a}{\"a}skel{\"a}inen and Olli Silv{\'e}n and Jari Hannuksela and Joseph R. Cavallaro},
  journal={2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)},
  year={2014},
  pages={8380-8384}
}
Exposed-datapath architectures yield small, low-power processors that trade instruction word length for aggressive compile-time scheduling and a high degree of instruction-level parallelism. In this paper, we present a general-purpose parallel accelerator consisting of a main processor and eight symmetric clusters, all in a single core. Use of a lightweight… CONTINUE READING