Parallel phase accumulator architecture for DDFS

  title={Parallel phase accumulator architecture for DDFS},
  author={Irwin Horowitz and G. S. la Rue},
  journal={2005 IEEE Workshop on Microelectronics and Electron Devices, 2005. WMED '05.},
A parallel architecture is described for a phase accumulator (PA) in a direct digital frequency synthesizer (DDFS) intended for space-based applications. A comparison is made between the parallel and pipelined PA architectures in a 0.18 mum CMOS technology. The parallel architecture dissipates about 1/3 less power while achieving performance at least as high as the pipelined architecture. The accumulator designs are hardened against latch-up, total dose effects and single-event upsets through… CONTINUE READING