Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs

@article{Naseer2008ParallelDE,
  title={Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs},
  author={R.. Naseer and Jeffrey W. Draper},
  journal={ESSCIRC 2008 - 34th European Solid-State Circuits Conference},
  year={2008},
  pages={222-225}
}
The range of SRAM multi-bit upsets (MBU) in sub-100 nm technologies is characterized using irradiation tests on two prototype ICs, developed in 90 nm commercial processes. Results reveal that MBU, as large as 13-bit, can occur in these technologies, limiting the efficacy of conventional SEC-DED error-correcting codes (ECC). A double-error correcting (DEC) ECC implementation technique suitable for SRAM applications is presented. Results show that this DEC scheme reduces errors by 98.5% compared… CONTINUE READING
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