Parallel and configurable turbo decoder implementation for 3GPP-LTE

@article{GonzalezPerez2013ParallelAC,
  title={Parallel and configurable turbo decoder implementation for 3GPP-LTE},
  author={Luis F. Gonzalez-Perez and Lennin C. Yllescas-Calderon and Ram{\'o}n Parra-Michel},
  journal={2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)},
  year={2013},
  pages={1-6}
}
An FPGA implementation of a highly parallel and configurable architecture for turbo decoding, compliant with the 3GPP-LTE standard is presented. This architecture can be integrated in reconfigurable platforms for software defined radio applications. A novel combination of the next iteration initialization method and the parallel and sliding window techniques is used in the MAP algorithm. This allows high throughput and reduced storage requirements, as compared to other solutions. Synthesis… CONTINUE READING

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