Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning

Abstract

While multi-core computing has become pervasive, scaling single core computations to multi-core computations remains a challenge. This paper aims to accelerate RTL and functional gate-level simulation in the current multi-core computing environment. This work addresses two types of partitioning schemes for multi-core simulation: functional, and domain-based. We discuss the limitations of functional partitioning, offered by new commercial multi-core simulators to speedup functional gate-level simulations. We also present a novel solution to increase RTL and functional gate-level simulation performance based on domain partitioning. This is the first known work that improves simulation performance by leveraging open source technology against commercial simulators.

DOI: 10.1109/ISVLSI.2014.47

13 Figures and Tables

Cite this paper

@article{Ahmad2014ParallelMV, title={Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning}, author={Tariq B. Ahmad and Maciej J. Ciesielski}, journal={2014 IEEE Computer Society Annual Symposium on VLSI}, year={2014}, pages={619-624} }