• Corpus ID: 225039904

ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics

  title={ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics},
  author={Rohit Agrawal and Kapil Ahuja and Dhaarna Maheshwari and Akash Kumar},
Routing of the nets in Field Programmable Gate Array (FPGA) design flow is one of the most time consuming steps. Although Versatile Place and Route (VPR), which is a commonly used algorithm for this purpose, routes effectively, it is slow in execution. One way to accelerate this design flow is to use parallelization. Since VPR is intrinsically sequential, a set of parallel algorithms have been recently proposed for this purpose (ParaLaR and ParaLarPD). These algorithms formulate the routing… 

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