• Corpus ID: 225039904

ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics

@article{Agrawal2020ParaLarHPF,
  title={ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics},
  author={Rohit Agrawal and Kapil Ahuja and Dhaarna Maheshwari and Akash Kumar},
  journal={ArXiv},
  year={2020},
  volume={abs/2010.11893}
}
Routing of the nets in Field Programmable Gate Array (FPGA) design flow is one of the most time consuming steps. Although Versatile Place and Route (VPR), which is a commonly used algorithm for this purpose, routes effectively, it is slow in execution. One way to accelerate this design flow is to use parallelization. Since VPR is intrinsically sequential, a set of parallel algorithms have been recently proposed for this purpose (ParaLaR and ParaLarPD). These algorithms formulate the routing… 

Figures and Tables from this paper

References

SHOWING 1-10 OF 26 REFERENCES
ParaLaR: A parallel FPGA router based on Lagrangian relaxation
TLDR
This paper proposes a scalable way of parallelizing the routing algorithm through Lagrangian relaxation, where the channel width constraints are relaxed by incorporating them into the objective function, and the result of the relaxation yields independent sub-problems that are solved using minimum Steiner tree algorithms.
ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method
TLDR
The LP framework of ParaLaR is used and the problem is solved using the primal–dual sub-gradient method that better exploits the problem properties and a better way to update the size of the step taken by this iterative algorithm is proposed.
VPR: A new packing, placement and routing tool for FPGA research
TLDR
In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which the authors can compare and presents placement and routing results on a new set of circuits more typical of today's industrial designs.
Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model
TLDR
A deterministic and parallel implementation of the VPR routability-driven router for FPGAs that considered two parallelization strategies: routing multiple nets in parallel; and routing one net at a time, while parallelizing the Maze Expansion step.
Circuit clustering for cluster-based FPGAs using novel multiobjective genetic algorithms
TLDR
Four alternative approaches based on MOGA methods are proposed in this research: RVPack is inspired by the stochastic feature that exists in Evolutionary Algorithms (EAs), andGGAPack, GGAPack2, DBPack and HYPack are proposed and developed, which are fully customised MogA-based circuit clustering methods.
The Lagrangian Relaxation Method for Solving Integer Programming Problems
TLDR
This paper is a review of Lagrangian relaxation based on what has been learned in the last decade and has led to dramatically improved algorithms for a number of important problems in the areas of routing, location, scheduling, assignment and set covering.
An 11/6-approximation algorithm for the network steiner problem
An instance of the Network Steiner Problem consists of an undirected graph with edge lengths and a subset of vertices; the goal is to find a minimum cost Steiner tree of the given subset (i.e.,
...
1
2
3
...