Packetization and routing analysis of on-chip multiprocessor networks

@article{Ye2004PacketizationAR,
  title={Packetization and routing analysis of on-chip multiprocessor networks},
  author={Terry Tao Ye and Luca Benini and Giovanni De Micheli},
  journal={Journal of Systems Architecture},
  year={2004},
  volume={50},
  pages={81-104}
}
Some current and most future systems-on-chips use and will use network architectures/protocols to implement onchip communication. On-chip networks borrow features and design methods from those used in parallel computing clusters and computer system area networks. They differ from traditional networks because of larger on-chip wiring resources and flexibility, as well as constraints on area and energy consumption (in addition to performance requirements). In this paper, we analyze different… CONTINUE READING
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