PTL: PRAM translation layer

Abstract

In this paper, we attempt to replace NAND Flash memory with PRAM, while PRAM initially targets replacing NOR Flash memory. To achieve it, we need to handle wear-leveling issue of PRAM since the maximum number of writes in PRAM is only 10. Thus, we have proposed PRAM Translation Layer (PTL) to resolve endurance problem for a PRAM-based storage system. We… (More)
DOI: 10.1016/j.micpro.2012.07.002

Topics

16 Figures and Tables

Cite this paper

@article{Choi2013PTLPT, title={PTL: PRAM translation layer}, author={Gyu Sang Choi and Byung-Won On and Kwonhue Choi and Sungwon Yi}, journal={Microprocessors and Microsystems - Embedded Hardware Design}, year={2013}, volume={37}, pages={24-32} }