PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer

@article{Beuningen2015PROTONAP,
  title={PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer},
  author={Anja von Beuningen and Luca Ramini and Davide Bertozzi and Ulf Schlichtmann},
  journal={JETC},
  year={2015},
  volume={12},
  pages={44:1-44:28}
}
Optical Networks-on-Chip (ONoCs) are a promising technology to overcome the bottleneck of low bandwidth of electronic Networks-on-Chip. Recent research discusses power and performance benefits of ONoCs based on their system-level design, while layout effects are typically overlooked. As a consequence, laser power requirements are inaccurately computed from the logic scheme but do not consider the layout. In this article, we propose PROTON+, a fast tool for placement and routing of 3D ONoCs… CONTINUE READING

Figures, Tables, Results, and Topics from this paper.

Key Quantitative Results

  • Using our tool, the required laser power of the system can be decreased by up to 94% compared to a state-of-the-art manually designed layout.
  • Using our tool, the required laser power of the system can be decreased by up to 94% compared to a state-of­the-art manually designed layout.

Citations

Publications citing this paper.
SHOWING 1-9 OF 9 CITATIONS

CustomTopo: A Topology Generation Method for Application-Specific Wavelength-Routed Optical NoCs

  • 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
  • 2018
VIEW 6 EXCERPTS
CITES METHODS & BACKGROUND

Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips

  • 2018 IEEE International Symposium on Circuits and Systems (ISCAS)
  • 2018
VIEW 5 EXCERPTS
CITES METHODS & BACKGROUND

Wavelength-Routed Optical NoCs : Design and EDA — State of the Art and Future Directions ( Invited Paper )

Tsun-Ming Tseng, Alexandre Truppel, Mengchu Li, Mahdi Nikdast, Ulf Schlichtmann
  • 2019
VIEW 1 EXCERPT
CITES BACKGROUND

Problems and challenges of emerging technology networks-on-chip: A review

  • Microprocessors and Microsystems - Embedded Hardware Design
  • 2017
VIEW 2 EXCERPTS
CITES METHODS

References

Publications referenced by this paper.
SHOWING 1-7 OF 7 REFERENCES