PROOFS: a fast, memory-efficient sequential circuit fault simulator

Abstract

This paper describes PROOFS, a super fast fault simulator for synchronous sequential circuits. PROOFS achieves high performance by combining all the advantages of <italic>differential fault simulation, single fault propagation,</italic> and <italic>parallel fault simulation</italic>, while minimizing their individual disadvantages. PROOFS minimizes the memory requirements, reduces the number of events that need to be evaluated, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs 6 to 67 times faster on the ISCAS sequential benchmarks.

DOI: 10.1145/123186.123396

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@article{Niermann1990PROOFSAF, title={PROOFS: a fast, memory-efficient sequential circuit fault simulator}, author={Thomas M. Niermann and Wu-Tung Cheng and Janak H. Patel}, journal={IEEE Trans. on CAD of Integrated Circuits and Systems}, year={1990}, volume={11}, pages={198-207} }