PRASE: An Approach for Program Reliability Analysis with Soft Errors

  title={PRASE: An Approach for Program Reliability Analysis with Soft Errors},
  author={Jianjun Xu and Rui Shen and QingPing Tan},
  journal={2008 14th IEEE Pacific Rim International Symposium on Dependable Computing},
Soft errors are emerging as a new challenge in computer applications. Current studies about soft errors mainly focus on the circuit and architecture level. Few works discuss the impact of soft errors on programs. This paper presents a novel approach named PRASE, which can analyze the reliability of a program with the effect of soft errors. Based on the simple probability theory and the corresponding assembly code of a program, we propose two models for analyzing the probabilities about error… CONTINUE READING


Publications citing this paper.
Showing 1-6 of 6 extracted citations

A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

IEEE Transactions on Parallel and Distributed Systems • 2016
View 4 Excerpts
Highly Influenced

SEInjector: A Dynamic Fault Injection Tool for Soft Errors on X86

2017 International Conference on Computer Systems, Electronics and Control (ICCSEC) • 2017
View 1 Excerpt

An approach to analyze effects of soft errors on program level

Mathematical and Computer Modelling • 2012
View 1 Excerpt

A Novel Optimum Data Duplication Approach for Soft Error Detection

2008 15th Asia-Pacific Software Engineering Conference • 2008
View 1 Excerpt


Publications referenced by this paper.
Showing 1-10 of 16 references


P. Shivakumar
Kistler and et al., “Modeling the effect of technology trends on the soft error rate of combinational logic”, Proc. Int’l Conf. Dependable Systems and Networks, pp. 389–399 • 2002
View 4 Excerpts
Highly Influenced

SoftArch: an architecture-level tool for modeling and analyzing soft errors

2005 International Conference on Dependable Systems and Networks (DSN'05) • 2005


N. J. Wang
Quek, T.M. Rafacz and et al., “Characterizing the Effects of Transient Faults on a Modern High- Performance Processor Pipeline”, Proc. Int’l Conf. Dependable Systems and Networks, pp. 61-70 • 2004
View 1 Excerpt

SER - History

J. F. Ziegler, H. Puchner
Trends, and Challenges: A Guide for Designing with Memory ICs”, Cypress Semiconductor Corp., San Jose, CA • 2004
View 1 Excerpt

and et al . , “ Fault Injection Techniques and Tools ”

T. K. Tsai
IEEE Computer • 2004


S. S. Mukherjee
Weaver and et al. “A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor”, Proc. 36th Int’l Symp. Microarchitecture, pp. 29-42 • 2003
View 1 Excerpt

Soft errors in advanced semiconductor devices-part I: the three radiation sources

R. C. Baumann
IEEE Trans. on Device and Materials Reliability, 1(1):17-22 • 2001
View 1 Excerpt

Similar Papers

Loading similar papers…