POWER7TM local clocking and clocked storage elements

@article{Warnock2010POWER7TMLC,
  title={POWER7TM local clocking and clocked storage elements},
  author={James D. Warnock and Leon J. Sigal and Dieter F. Wendel and K. Paul Muller and Joshua Friedrich and Victor V. Zyuban and Ethan H. Cannon and A. J. KleinOsowski},
  journal={2010 IEEE International Solid-State Circuits Conference - (ISSCC)},
  year={2010},
  pages={178-179}
}
The design of the clocked storage elements (CSEs) and associated local clocking circuitry is a critical consideration for modern microprocessor projects[1], and the POWER7™ chip[2], designed in a 45nm silicon-on-insulator (SOI) technology, was no exception. The digital logic contained over 2M CSEs, and the design of these elements had a major impact not… CONTINUE READING