POSTER: Statement Reordering to Alleviate Register Pressure for Stencils on GPUs

Abstract

Compute-intensive GPU architectures allow the use of high-order 3D stencils for better computational accuracy. These stencils are usually compute-bound. While current state-of-the-art register allocators are satisfactory for most applications, they are unable to effectively manage register pressure for such complex high-order stencils, resulting in a sub… (More)
DOI: 10.1109/PACT.2017.40

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