PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess

Abstract

This paper describes PGR, an architectural technique to reduce dynamic power via GlitchLess or to improve performance via clock skew scheduling (CSS) and delay padding (DP). It is integrated into VPR 5.0, and is invoked after the routing stage. We use programmable delay elements (PDEs) as a novel architecture modification to insert delay on FF clock inputs… (More)
DOI: 10.1109/FPT.2009.5377666

13 Figures and Tables

Cite this paper

@article{Dong2009PGRPA, title={PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess}, author={Xiao Dong and Guy Lemieux}, journal={2009 International Conference on Field-Programmable Technology}, year={2009}, pages={88-95} }