PGCapping: Exploiting power gating for power capping and core lifetime balancing in CMPs

@article{Ma2012PGCappingEP,
  title={PGCapping: Exploiting power gating for power capping and core lifetime balancing in CMPs},
  author={Kai Ma and Xiaorui Wang},
  journal={2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)},
  year={2012},
  pages={13-22}
}
Optimizing the performance of a chip multiprocessor (CMP) within a power cap has recently received a lot of attention. However, most existing solutions rely solely on DVFS, which is anticipated to have only limited actuation ranges in the future. Power gating shuts down idling cores in a CMP, such that more power can be shifted to the cores that run applications for better CMP performance. However, current preliminary studies on integrating the two knobs focus on deciding the power gating and… CONTINUE READING
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