PERFECT case studies demonstrating order of magnitude reduction in power consumption

Abstract

We propose three methods for reducing power consumption in high-performance FPGAs (field programmable gate arrays). We show that by using continuous hierarchy memory, lightweight checks, and lower chip voltage for near-threshold voltage computation, we can both reduce power consumption and increase reliability without a decrease in throughput. We have implemented these techniques in two different, realistic wide-area motion imagery algorithms on FPGAs. We demonstrated greatly improved performance/efficiency compared to two flight-tested platforms, getting up to a 250X reduction in power use (measured in giga operations per second per watt). This paper summarizes these two case studies.

DOI: 10.1109/HPEC.2016.7761612

Cite this paper

@article{Wittenberg2016PERFECTCS, title={PERFECT case studies demonstrating order of magnitude reduction in power consumption}, author={David K. Wittenberg and Edin Kadric and Andr{\'e} DeHon and Jonathan Edwards and Jeffrey Smith and Silviu Chiricescu}, journal={2016 IEEE High Performance Extreme Computing Conference (HPEC)}, year={2016}, pages={1-7} }