PCI express and advanced switching: evolutionary path to building next generation interconnects

@article{Mayhew2003PCIEA,
  title={PCI express and advanced switching: evolutionary path to building next generation interconnects},
  author={David Mayhew and Venkata Krishnan},
  journal={11th Symposium on High Performance Interconnects, 2003. Proceedings.},
  year={2003},
  pages={21-29}
}
  • D. Mayhew, V. Krishnan
  • Published 15 September 2003
  • Computer Science
  • 11th Symposium on High Performance Interconnects, 2003. Proceedings.
With processor and memory technologies pushing the performance limit, the bottleneck is clearly shifting towards the system interconnect. Any solution that addresses the PCI bus-based interconnect, which has serious scalability problems, must also protect the huge legacy infrastructure. PCI Express provides such an evolutionary approach and allows a smooth migration towards building a highly scalable next generation interconnect. Advanced switching further boosts the capabilities of PCI Express… 
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73 Citations
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73 Citations

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TLDR
A framework to provide QoS based on bandwidth, latency, and jitter over AS employing the mechanisms provided by AS is proposed and several implementations for the output scheduling mechanism are presented.
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TLDR
The final results confirm that the use of ASI for supporting I/O disaggregation does not result in sub-optimal utilization of the GigE NIC and shows a marginal effect on the application's latency, but contrary to expectations, the throughput was significantly impacted.
Prototyping Efficient Interprocessor Communication Mechanisms
TLDR
An efficient FPGA-based platform that is developed and used for research and experimentation on high speed interprocessor communication, network interfaces and interconnects, and shows how software can take advantage of the provided features, but also expose the weaknesses of the system.
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TLDR
This paper implements the PCIe based interconnection network system with low latency, low power, RDMA, and other characteristics using Socket API which is mainly used in the user-level application program rather than the existing MPI and PGAS model interfaces.
High performance architectures for Chip-to-Chip Communications on Network Line Cards
TLDR
Performance results show that both 3D-interconnects achieve high throughput, low latency results surpassing other common interconnects currently deployed, and were able to sustain high traffic load while keeping low failure rates and high bandwidth utilization levels.
Studying Several Proposals for the Adaptation of the DTable Scheduler to Advanced Switching
TLDR
This paper proposes several possible modifications to the original AS table scheduler in order to implement the Deficit Table (DTable) scheduler, which works properly with variable packet sizes and allows to partially decouple the bandwidth and latency assignments.
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References

SHOWING 1-10 OF 34 REFERENCES
Layered shortest path (LASH) routing in irregular system area networks
TLDR
This paper proposes a method that guarantees shortest path routing and in-order delivery, and that uses virtual channels for deadlock avoidance, and presents a theoretical upper bound on the number of virtual channels needed, and demonstrates that the actual number ofvirtual channels is very low even for large networks.
Routing lookups in hardware at memory access speeds
  • Pankaj Gupta, Steven Lin, N. McKeown
  • Computer Science
    Proceedings. IEEE INFOCOM '98, the Conference on Computer Communications. Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies. Gateway to the 21st Century (Cat. No.98
  • 1998
TLDR
This work presents a route lookup mechanism that when implemented in a pipelined fashion in hardware, can achieve one route lookup every memory access; much faster than current commercially available routing lookup schemes.
Myrinet: A Gigabit-per-Second Local Area Network
TLDR
The Myrinet local area network employs the same technology used for packet communication and switching within massively parallel processors, but with the highest performance per unit cost of any current LAN.
The Quadrics Network: High-Performance Clustering Technology
TLDR
The Quadrics network extends the native operating system in processing nodes with a network operating system and specialized hardware support in the network interface and provides network fault tolerance.
Congestion control
TLDR
Congestion is an inherent problem for networks with multiple user access when the load exceeds what can be handled even with optimal routing, so window flow control and rate flow control schemes are discussed.
End-to-end congestion control for infiniband
  • J. Santos, Y. Turner, G. Janakiraman
  • Computer Science
    IEEE INFOCOM 2003. Twenty-second Annual Joint Conference of the IEEE Computer and Communications Societies (IEEE Cat. No.03CH37428)
  • 2003
TLDR
This paper proposes an end-to-end congestion control scheme that avoids congestion spreading, delivers high throughput, and prevents flow starvation, and couples a simple switch-based ECN packet marking mechanism appropriate for typical SAN switches with small input buffers with source response mechanism that uses rate control combined with a window limit.
A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code
TLDR
The proposed transmission code translates each source byte into a constrained 10-bit binary sequence which has excellent performance parameters near the theoretical limits for 8B/10B codes.
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
TLDR
A deadlock-free routing algorithm can be generated for arbitrary interconnection networks using the concept of virtual channels, which is used to develop deadlocked routing algorithms for k-ary n-cubes, for cube-connected cycles, and for shuffle-exchange networks.
Credit-based flow control for ATM networks
TLDR
The credit-based mechanism proposed by the authors provides flow control tailored to ATM networks that uses links efficiently, minimizes delay, and guarantees no cell loss due to congestion.
Classless Inter-Domain Routing (CIDR): an Address Assignment and Aggregation Strategy
This memo discusses strategies for address assignment of the existing IP address space with a view to conserve the address space and stem the explosive growth of routing tables in default-route-free…
...
1
2
3
4
...