PCB via to trace return loss optimization for >25Gbps serial links

@article{Zhang2014PCBVT,
  title={PCB via to trace return loss optimization for >25Gbps serial links},
  author={Ji Zhang and Jane Lim and Wei Yao and Kelvin Qiu and Rick Brooks},
  journal={2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)},
  year={2014},
  pages={619-624}
}
High speed serial links usually have extremely tight requirement on the quality of the signal channels, in terms of insertion loss and return loss. Along with an end-to-end channel design, the transition from plated-through-hole (PTH) via to fan-out traces on printed circuit board (PCB) creates unavoidable impedance discontinuity, which greatly impacts the channel return loss performance. It is important to understand and model this discontinuity for optimization purpose. This paper discusses… CONTINUE READING