P 1-17 Time Behavioral Model for Phase-Domain ADPLL based Frequency Synthesizer

In this paper, we present a Time Behavioral Model of a recently proposed Phase-Domain All-Digital PhaseLocked Loop (ADPLL) for RF applications. This model can be easily implemented, and results in a versatile and fast ADPLL simulator that enables to study many aspects of the PLL, e.g. transient responses, steady states, limit cycles, or to perform… CONTINUE READING