Overview study on fault modeling and test methodology development for FinFET-based memories

@article{Tshagharyan2015OverviewSO,
  title={Overview study on fault modeling and test methodology development for FinFET-based memories},
  author={G. Tshagharyan and Gurgen Harutunyan and Samvel K. Shoukourian and Yervant Zorian},
  journal={2015 IEEE East-West Design & Test Symposium (EWDTS)},
  year={2015},
  pages={1-4}
}
Rapidly developing FinFET technology, alternative to the conventional planar technology, plays an important role in routing modern silicon industry. Due to unique structure of FinFET transistors the defect types and resulting fault models is different for FinFET transistors compared to planar ones. As a result the well-established flow used for embedded test and repair solutions development for MOSFET-based memories fails to be smoothly deployed for FinFET-based memories as well. Thus there is… CONTINUE READING

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