Overview of ITRI PAC project - from VLIW DSP processor to multicore computing platform

@article{Lin2008OverviewOI,
  title={Overview of ITRI PAC project - from VLIW DSP processor to multicore computing platform},
  author={Tay-Jyi Lin and Chun-Nan Liu and Shau-Yin Tseng and Yuan-Hua Chu and An-Yeu Wu},
  journal={2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)},
  year={2008},
  pages={188-191}
}
The Industrial Technology Research Institute (ITRI) PAC (parallel architecture core) project was initiated in 2003. The target is to develop a low-power and high-performance programmable SoC platform for multimedia applications. In the first PAC project phase (2004-2006), a 5-way VLIW DSP (PACDSP) processor has been developed with our patented distributed & ping-pong register file and variable-length VLIW encoding techniques. A dual-core PAC SoC, which is composed of a PACDSP core and an ARM9… CONTINUE READING
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2 Excerpts

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