Overview of ITRI PAC project - from VLIW DSP processor to multicore computing platform

  title={Overview of ITRI PAC project - from VLIW DSP processor to multicore computing platform},
  author={Tay-Jyi Lin and Chun-Nan Liu and Shau-Yin Tseng and Yuan-Hua Chu and An-Yeu Wu},
  journal={2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)},
The Industrial Technology Research Institute (ITRI) PAC (parallel architecture core) project was initiated in 2003. The target is to develop a low-power and high-performance programmable SoC platform for multimedia applications. In the first PAC project phase (2004-2006), a 5-way VLIW DSP (PACDSP) processor has been developed with our patented distributed & ping-pong register file and variable-length VLIW encoding techniques. A dual-core PAC SoC, which is composed of a PACDSP core and an ARM9… CONTINUE READING
Highly Cited
This paper has 54 citations. REVIEW CITATIONS
37 Citations
6 References
Similar Papers


Publications citing this paper.
Showing 1-10 of 37 extracted citations

54 Citations

Citations per Year
Semantic Scholar estimates that this publication has 54 citations based on the available data.

See our FAQ for additional information.


Publications referenced by this paper.
Showing 1-6 of 6 references

Area-efficient register organization for fully-synthesizable VLIW DSP cores

  • T. J. Lin, P. C. Hsiao, C. W. Liu, C. W. Jen
  • International Journal of Electrical Engineering…
  • 2006
1 Excerpt

DVFS SoC architecture and implementation

  • C. Y. Lai, J. H. Lin, Y. F. Wang
  • SoC Technology Journal, vol. 3, pp.84-91, 2005 I…
  • 2005
1 Excerpt

Design & implementation of a high-performance & complexityeffective VLIW DSP for multimedia applications

  • T. J. Lin, P. C. Hsiao, S. K. Chen, Y. T. Kuo, C. W. Liu
  • to appear in Journal of VLSI Signal Processing
2 Excerpts

Similar Papers

Loading similar papers…