Overlay aware interconnect and timing variation modeling for Double Patterning Technology

@article{Yang2008OverlayAI,
  title={Overlay aware interconnect and timing variation modeling for Double Patterning Technology},
  author={Jae-Seok Yang and David Z. Pan},
  journal={2008 IEEE/ACM International Conference on Computer-Aided Design},
  year={2008},
  pages={488-493}
}
As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, we present an efficient modeling of timing variation with overlay which is inevitable for DPT. Our work makes it possible to analyze timing with overlay variables. Since the variation of metal space caused by overlay results in coupling capacitance variation, we first model metal spacing variation with individual overlay… CONTINUE READING
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