Overlay as the key to drive wafer scale 3D integration
@article{Steen2007OverlayAT, title={Overlay as the key to drive wafer scale 3D integration}, author={Steven E. Steen and Douglas LaTulipe and Anna W. Topol and David J. Frank and Kevin Belote and Dominick Posillico}, journal={Microelectronic Engineering}, year={2007}, volume={84}, pages={1412-1415} }
21 Citations
Wafer-to-Wafer Alignment for Three-Dimensional Integration: A Review
- Engineering, BusinessJournal of Microelectromechanical Systems
- 2011
This paper presents a review of the wafer-to-wafer alignment used for 3-D integration. This technology is an important manufacturing technique for advanced microelectronics and microelectromechanical…
3D Process Technology Considerations
- Computer Science
- 2010
This chapter outlines the basic process considerations that designers need to be aware of: strata orientation, inter-strata alignment, bonding-interface design, TSV dimensions, and integration with CMOS processing.
Wafer Level High Density Hybrid Bonding for High Performance Computing
- Engineering2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
- 2020
Recently, there has been an increasing use of 3D stack integration for high-performance computing applications. Wafer-to-wafer (W2W) hybrid bonding is a key technology in 3D stacking integration…
3D Fabrication Options for High-Performance CMOS Technology
- Computer Science
- 2008
Three dimensional (3D) integration technologies offer the promise of increasing system performance even in the absence of scaling, and 2D can dramatically increase the number of interconnects and therefore increase the aggregate communication bandwidth between chips, and 3D can allow dissimilar functions, technologies, and materials to be integrated.
Wafer-level 3D integration technology
- EngineeringIBM J. Res. Dev.
- 2008
An overview of wafer-level three-dimensional integration technology is provided, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits.
Chapter 9 3 D Fabrication Options for High-Performance CMOS Technology
- Computer Science
- 2008
Three dimensional (3D) integration technologies offer the promise of increasing system performance even in the absence of scaling, and 2D can dramatically increase the number of interconnects and therefore increase the aggregate communication bandwidth between chips, and 3D can allow dissimilar functions, technologies, and materials to be integrated.
Micro/Nanoscale 3D Assembly by Rolling, Folding, Curving, and Buckling Approaches
- Materials ScienceAdvanced materials
- 2019
The latest progress in the area of micro/nanoscale 3D assembly, covering the various classes of methods through rolling, folding, curving, and buckling assembly, is discussed, focusing on the design concepts, principles, and applications of different methods, followed by an outlook on the remaining challenges and open opportunities.
100 mm wafer-scale InP-based (λ=1.6 μm) epitaxial transfer for hybrid silicon evanescent lasers
- Engineering2008 58th Electronic Components and Technology Conference
- 2008
We report the large epitaxial transfer of 100 mm InP/InGaAs/InP wafers to Silicon-on-insulator (SOI) substrates through a low-temperature (300degC) O2 plasma- assisted wafer bonding process.…
An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits
- Computer ScienceIEEE Transactions on Very Large Scale Integration (VLSI) Systems
- 2016
An evaluation framework to assess the potential benefits of feature-level heterogeneous integration (HGI) in nanoscale VLSI circuits is developed and it is demonstrated that the HGI misalignment area penalties can be drastically reduced using posttransfer fin trimming.
Infrared differential interference contrast microscopy for 3D interconnect overlay metrology.
- Materials ScienceOptics express
- 2013
One of the main challenges for 3D interconnect metrology of bonded wafers is measuring through opaque silicon wafers using conventional optical microscopy. We demonstrate here the use infrared…
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