Overlay as the key to drive wafer scale 3D integration

@article{Steen2007OverlayAT,
  title={Overlay as the key to drive wafer scale 3D integration},
  author={Steven E. Steen and Douglas LaTulipe and Anna W. Topol and David J. Frank and Kevin Belote and Dominick Posillico},
  journal={Microelectronic Engineering},
  year={2007},
  volume={84},
  pages={1412-1415}
}

Figures from this paper

Wafer-to-Wafer Alignment for Three-Dimensional Integration: A Review
This paper presents a review of the wafer-to-wafer alignment used for 3-D integration. This technology is an important manufacturing technique for advanced microelectronics and microelectromechanical
3D Process Technology Considerations
TLDR
This chapter outlines the basic process considerations that designers need to be aware of: strata orientation, inter-strata alignment, bonding-interface design, TSV dimensions, and integration with CMOS processing.
Wafer Level High Density Hybrid Bonding for High Performance Computing
Recently, there has been an increasing use of 3D stack integration for high-performance computing applications. Wafer-to-wafer (W2W) hybrid bonding is a key technology in 3D stacking integration
3D Fabrication Options for High-Performance CMOS Technology
TLDR
Three dimensional (3D) integration technologies offer the promise of increasing system performance even in the absence of scaling, and 2D can dramatically increase the number of interconnects and therefore increase the aggregate communication bandwidth between chips, and 3D can allow dissimilar functions, technologies, and materials to be integrated.
Wafer-level 3D integration technology
TLDR
An overview of wafer-level three-dimensional integration technology is provided, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits.
Chapter 9 3 D Fabrication Options for High-Performance CMOS Technology
TLDR
Three dimensional (3D) integration technologies offer the promise of increasing system performance even in the absence of scaling, and 2D can dramatically increase the number of interconnects and therefore increase the aggregate communication bandwidth between chips, and 3D can allow dissimilar functions, technologies, and materials to be integrated.
Micro/Nanoscale 3D Assembly by Rolling, Folding, Curving, and Buckling Approaches
TLDR
The latest progress in the area of micro/nanoscale 3D assembly, covering the various classes of methods through rolling, folding, curving, and buckling assembly, is discussed, focusing on the design concepts, principles, and applications of different methods, followed by an outlook on the remaining challenges and open opportunities.
100 mm wafer-scale InP-based (λ=1.6 μm) epitaxial transfer for hybrid silicon evanescent lasers
We report the large epitaxial transfer of 100 mm InP/InGaAs/InP wafers to Silicon-on-insulator (SOI) substrates through a low-temperature (300degC) O2 plasma- assisted wafer bonding process.
An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits
TLDR
An evaluation framework to assess the potential benefits of feature-level heterogeneous integration (HGI) in nanoscale VLSI circuits is developed and it is demonstrated that the HGI misalignment area penalties can be drastically reduced using posttransfer fin trimming.
Infrared differential interference contrast microscopy for 3D interconnect overlay metrology.
One of the main challenges for 3D interconnect metrology of bonded wafers is measuring through opaque silicon wafers using conventional optical microscopy. We demonstrate here the use infrared
...
...

References

SHOWING 1-10 OF 18 REFERENCES
Creating 3D circuits using transferred films
TLDR
This work has developed an interconnection technology that allows layers to be electrically connected to one another and can be placed anywhere on the die, which gives this technology a unique advantage over other existing 3D interconnect techniques.
An investigation of wafer-to-wafer alignment tolerances for three-dimensional integrated circuit fabrication
We report results of an analysis of alignment data obtained from wafers aligned and oxide bonded in our facility. A description of an advanced wafer alignment tool currently under development is also
First-order performance prediction of cache memory with wafer-level 3D integration
TLDR
A simulator based on analytical models is used to build an optimal processor-memory configuration for two designs: a graphics processor and a microprocessor, with emphasis on large caches in deep-submicron technologies.
Fabrication of three-dimensional IC using `cumulatively bonded IC' (CUBIC) technology
A technology is proposed for the fabrication of three-dimensional integrated circuits (3D-ICs) having a large number of device layers, referred to as `cumulatively bonded IC' (CUBIC) technology
A new wafer-bonder of ultra-high precision using surface activated bonding (SAB) concept
A robot-controlled wafer bonding machine was developed for the bonding of different sizes of wafers ranging up to 8 inches diameter. The features of this equipment are such that: (1) After the
3D CMOS SOL for high performance computing
TLDR
A new three-dimensional CMOS-SOI on SOI technology is presented, design methodologies are proposed for this technology and last, a comparison is carried out between 2D and 3D designs.
3D CMOS SOI for high performance computing
TLDR
A new three-dimensional CMOS-SOI technology is presented, design methodologies are proposed for this technology and last, a comparison is carried out between 2D and 3D designs.
Thermal analysis of three-dimensional (3-D) integrated circuits (ICs)
  • A. Rahman, R. Reif
  • Engineering
    Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461)
  • 2001
In this paper, we examine the thermal issues in 3-D ICs by system-level modeling of power dissipation and analytical and numerical modeling of deviceand package-level heat removal. We find that for
Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs
  • R. Patti
  • Engineering
    Proceedings of the IEEE
  • 2006
Three-dimensional integrated circuits (3-D ICs) offer significant improvements over two-dimensional circuits, and promise a solution to the severe problems that are being, and will be, encountered as
2.5-dimensional VLSI system integration
TLDR
This paper investigates a new VLSI integration paradigm, the so-called 2.5-dimensional (2. 5-D) integration scheme, using this scheme, a VLSi system is implemented as a three-dimensional stacking of monolithic chips.
...
...