Organizing the last line of defense before hitting the memory wall for CMPs

@article{Liu2004OrganizingTL,
  title={Organizing the last line of defense before hitting the memory wall for CMPs},
  author={Chun Liu and Anand Sivasubramaniam and Mahmut T. Kandemir},
  journal={10th International Symposium on High Performance Computer Architecture (HPCA'04)},
  year={2004},
  pages={176-185}
}
The last line of defense in the cache hierarchy before going to off-chip memory is very critical in chip multiprocessors (CMPs) from both the performance and power perspectives. We investigate different organizations for this last line of defense (assumed to be L2 in this article) towards reducing off-chip memory accesses. We evaluate the trade-offs between private L2 and address-interleaved shared L2 designs, noting their individual benefits and drawbacks. The possible imbalance between the L2… CONTINUE READING

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Key Quantitative Results

  • Our results show as much as 42.50% improvement in IPC over the private organization (with 11.52% on the average), and as much as 42.22% improvement over the shared interleaved organization (with 9.76% on the average).1.
  • Our results show as much as 42.50% improvement in IPC over the private organization (with 11.52% on the average), and as much as 42.22% improvement over the traditional shared organization (with 9.76% on the average).

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Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs

  • C. Liu, A. Sivasubramaniam, M. Kandemir
  • Penn State University Tech Report CSE-03-019,
  • 2003
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