Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits

  title={Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits},
  author={Duo Liu and Cunxi Yu and Xiangyu Zhang and Daniel E. Holcomb},
  journal={2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
Layout-level gate camouflaging has attracted interest as a countermeasure against reverse engineering of combinational logic. In order to minimize area overhead, typically only a subset of gates in a circuit are camouflaged, and each camouflaged gate layout can implement a few different logic functions. The security of camouflaging relies on the difficulty of learning the overall combinational logic function without knowing which logic functions the camouflaged gates implement. 
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