Optoelectronic-cache memory system architecture.


We present an investigation of the architecture of an optoelectronic cache that can integrate terabit optical memories with the electronic caches associated with high-performance uniprocessors and multiprocessors. The use of optoelectronic-cache memories enables these terabit technologies to provide transparently low-latency secondary memory with frame sizes comparable with disk pages but with latencies that approach those of electronic secondary-cache memories. This enables the implementation of terabit memories with effective access times comparable with the cycle times of current microprocessors. The cache design is based on the use of a smart-pixel array and combines parallel free-space optical input-output to-and-from optical memory with conventional electronic communication to the processor caches. This cache and the optical memory system to which it will interface provide a large random-access memory space that has a lower overall latency than that of magnetic disks and disk arrays. In addition, as a consequence of the high-bandwidth parallel input-output capabilities of optical memories, fault service times for the optoelectronic cache are substantially less than those currently achievable with any rotational media.

DOI: 10.1364/AO.35.002449

Extracted Key Phrases

10 Figures and Tables

Cite this paper

@article{Chiarulli1996OptoelectroniccacheMS, title={Optoelectronic-cache memory system architecture.}, author={Donald M. Chiarulli and S. P. Levitan}, journal={Applied optics}, year={1996}, volume={35 14}, pages={2449-56} }