Optimizing nanoscale MOSFET architecture for low power analog/RF applications

@article{Ghosh2013OptimizingNM,
  title={Optimizing nanoscale MOSFET architecture for low power analog/RF applications},
  author={Dipak Kumar Ghosh and Mukta Singh Parihar and Abhinav Kranti},
  journal={2013 IEEE 5th International Nanoelectronics Conference (INEC)},
  year={2013},
  pages={22-23}
}
This work reports on possible ways of improving analog/RF performance metrics, through device structure optimization, for low power applications. It is shown that underlap source/drain (S/D) design and junctionless transistor architecture can both yield improved analog/RF figures of merit in comparison to conventional abrupt source/drain MOSFETs. Junctionless devices overcome the gain-bandwidth trade-off associated with analog design. The results are significant for RFICs in emerging ultra-low… CONTINUE READING

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