On the Physical Behavior of Cryogenic IV and III–V Schottky Barrier MOSFET Devices
- Mike Schwarz, Laurie E. Calvet, John P. Snyder, Tillmann Krauss, Udo Schwalke, Alexander Kloes
- IEEE Transactions on Electron Devices
- 2017
1 Excerpt
Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance
- Published 2003 in IEEE Electron Device Letters
Abstract
For the first time, mixed mode simulation is used to optimize the design of ultrathin-body dual-gate metal source/drain 25-nm CMOS, showing an advantage for source/drain-to-gate underlap, rather than overlap. The effect of source/drain workfunction and silicon thickness on the optimal underlap, and on the resulting circuit speed, is examined. A substantial… (More)