Corpus ID: 19223159

Optimization of logic area for System on Programmable Chip based on hardware-software partitioning

  title={Optimization of logic area for System on Programmable Chip based on hardware-software partitioning},
  author={Mehdi Jemai and S. Dimassi and B. Ouni and A. Mtibaa},
  • Mehdi Jemai, S. Dimassi, +1 author A. Mtibaa
  • Published 2014
  • T In this paper, we propose an approach based on hardware-software partitioning to minimize logic area of a SOPC circuit "System on a Programmable Chip". This approach minimizes the SOPC area while satisfying a time constraint. To minimize this area, we propose an algorithm to determine the critical path with the largest number of hardware tasks in a given data flow graph. Once these hardware tasks are determined, they will be implemented on the software. In this way we minimize the number of… CONTINUE READING
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