Optimization of high-level design edge detect filter for video processing system on FPGA

@article{Alareqi2017OptimizationOH,
  title={Optimization of high-level design edge detect filter for video processing system on FPGA},
  author={Mohammed Alareqi and Rachid Elgouri and Khalid Mateur and A. Zemmouri and A. Mezouari and Laamari Hlou},
  journal={2017 Intelligent Systems and Computer Vision (ISCV)},
  year={2017},
  pages={1-8}
}
This paper presents the design and the implementation of edge detect filter is optimized for video processing applications on FPGAs. It outlines efficient hardware architecture of spatial filtering (edge detection) for video processing system. This architecture offers a substitute through a graphical user interface that mixes MATLAB, Simulink and Xilinx… CONTINUE READING